Digital systems typically comprise a collection of circuit boards, each implementing a few major functions. The circuit boards, together, interact to produce a behavior that is required of the composite system.
When such a system fails to function properly, testing proceeds in a series of steps designed to isolate the source of a fault. The first step often is a simple go-no go test of the system as a whole, to confirm that there actually is a system fault. Sometimes such a test reveals that the system is functioning properly, but that the failure is caused by an external factor, such as an operator error or a defective power source.
Assuming that the system itself is found to be faulty, however, the next step is to isolate the fault to a particular circuit board. Circuit board level diagnosis is achieved either by running a set of functional tests which exercise the boards individually, or by replacing the boards successively with known operational boards until the system once again functions properly. Since the number of circuit boards in most systems is small, board swapping is fast and can be performed in the field.
The system is now repaired, but one is left with at least one circuit board that does not operate. Economics dictates that the board be repaired, however, the techniques that apply to board-level fault isolation are not practical for component-level diagnosis for several reasons. First, because each circuit board tends to contain a relatively large number of components, the number of different tests corresponding to the various components that would have to be performed to isolate a fault is prohibitive. Second, there are many different components which, when faulty, produce identical symptoms at fundamental outputs of the circuit board. In addition, components on a production circuit board usually are soldered in place. Component swapping thus is impractical. A method for locating a faulty component without requiring disassembly of the circuit board is therefore required.
Thus, computer guided fault isolation, also termed computer-guided probing, has been developed. In computer guided probing, the technician is directed in the placement of a logic probe back from a failing edge connector on the circuit board until the source of the circuit board fault is located. As the technician probes each node of the circuit, the node is exercised by a stimulus pattern signal injected at any circuit node on the board under test or at the microprocessor signal lines on the board. In the latter case, the microprocessor is electrically replaced with a special interface pod which is connected to a troubleshooting device, such as a Fluke 9020A troubleshooter Responses to the stimulus pattern signals at the circuit nodes are compared with pattern signals developed by an operational unit under test (UUT), to identify the source of a fault at the node being probed or alternatively to recommend the next node to be probed.
Computer guided fault isolation techniques that have been applied to circuit board troubleshooting have drawbacks that become aggravated as complexity of the UUT increases. Node-to-node probing by the technician under the guidance of visual prompting by the computer is a very slow process, because the number of nodes involved is substantial in most microprocessor based systems. Furthermore, guided fault isolation is inefficient; the "cleverness" and "intuition" of an experienced technician are not implemented in the computer based methodology. For example, although prior art guided fault isolation systems apply a single stimulus pattern signal to the UUT, e.g., circuit board, to exercise all nodes, all nodes in practice are not reliably testable using a common stimulus pattern. The stimulus pattern should ideally be tailored to each node whose response is being probed. Furthermore, an experienced technician does not probe every node of each circuit board undergoing troubleshooting. To expedite testing, the technician, based on his experience, begins recognizing failure patterns and formulating diagnoses and upon recognizing that certain nodes in a particular UUT have failed, probes certain other "companion" nodes, to confirm his diagnosis. His probing may furthermore be limited to particular areas of the circuit board based upon the initial diagnosis that only particular functions of the circuit board have failed. Furthermore, the technician, unlike guided fault isolation systems of the prior art, is capable of testing circuit components and functions on bidirectional signal lines that commonly exist in microprocessor based UUTs.
Accordingly, one object of the invention is to provide an improved method of and system for isolating circuit faults in a UUT.
An additional object is to provide computer aided guided fault isolation on bidirectional signal lines such as those common with microprocessor based UUTs.
Another object is to provide guided fault isolation that is controlled by a user programmable computer.
A further object is to provide guided fault isolation wherein clues to the technician are developed by a computer as testing progresses, to expedite fault source location.
A further object is to provide a method of and system for guided fault isolation during circuit board troubleshooting wherein circuit nodes are stimulated by different stimulus pattern signals that are tailored for each node being probed.
A further object is to provide guided fault isolation incorporating "artificial intelligence" whereby failure modes of each type of UUT are stored over time and processed to generate prompting of the technician on the basis of established failure mode patterns.
An additional object is to provide optimized guided fault isolation wherein a variety of different types of node responses to stimulii are stored and compared to measured responses.
A further object is to provide a guided fault isolation system wherein the technician can apply intuition during testing.